With Intel, it can be hard to keep up with all of the CPUs with the word “lake” in their names. It’s selling Raptor Lake, with Arrow Lake set to replace it later this year. Afterward, it’s got an architecture named Panther Lake, due in 2025. Not much is known about Panther Lake other than it is likely a mobile platform similar to Meteor Lake and Lunar Lake, which are mobile-only. Now, a user on X has leaked a schematic of the processor, core configurations, and power figures for Panther Lake, giving us the first hint about what it may offer.
There’s a lot to parse here as Intel is beginning to leapfrog itself with so many new architectures in the pipeline, and they are all different. The leaked information covers two variants of Panther Lake mobile, U and H, which are “ultra-portable” and mainstream SKUs in Intel parlance. The leaked info details one Panther Lake-U processor and two Panther Lake-H CPUs, with varying core counts and iGPU Xe cores.
One of the most notable tidbits of info is that the low-power cores present in Meteor Lake but removed from Lunar Lake are returning in Panther Lake and are now four instead of two. Intel said they removed them in Lunar Lake to improve efficiency, so we’re surprised to see them return so soon.
The new info includes three SKUs: the low-power U processor is rated at 15W, and the two mainstream H CPUs consume 25W. The high-end H CPU sports a 16-core design with 12 Xe cores, which seems like a formidable combo at 25W and might even be mislabeled, according to TechRadar. Given its beefy specs, it could be a P-series or high-end gaming chip, not an H-series. Note that these are next-gen Xe cores, too, using Intel’s Celestial architecture, which we have heard nothing about. It has yet to release its second-gen architecture, Battlemage, but it will appear first in Lunar Lake later this year. Celestial is its third-generation design, followed by an architecture named Druid at some point in the future.
There’s also a 16-core H CPU with just 4 Xe cores, and the Panther Lake U processor removes the efficiency cores in favor of four P-cores and four “low-power island” cores along with 4 Xe cores.
The included schematic features five tiles, with two labeled as passive just to take up space on the package. Intel also did this on Lunar Lake, going with two active dies and a filler die in the corner. Meteor Lake used four tiles that filled the entire package. Clearly, Intel is taking advantage of the disaggregated nature of these tile-based designs to make its tiles as big as they need to be instead of forcing them to conform to specific dimensions.